Not Applicable.
Not Applicable.
The present embodiments relate to digital data circuits, and are more particularly directed to systems presenting multiple clocks with a single data bus.
In many digital data systems or circuits, the system includes a single data bus and a corresponding single clock signal, where a high (or possibly low) clock transition designates the proper sampling time for the corresponding data; however, in some systems, such as the gigabit internet standard identified by IEEE 802.3Z, the historic evolution of the system has resulted in a single data bus, but with two out of phase clocks. More particularly, part of the data on the gigabit internet standard data bus is properly sampled according to a first of these two clocks while a different part of the data on that bus is properly sampled according to a second of these two clocks. While this interface is provided as part of a standard and is somewhat prevalent, it often creates complexities or difficulties for systems that connect to this interface because most often such systems have been developed or are developed with an internal expectation of a single data bus and a single corresponding clock signal.
One prior art approach has been attempted in an effort to convert the dual clock system provided by an interface such as the gigabit internet standard to a single clock signal. More particularly, this prior art approach implements a phase locked loop (xe2x80x9cPLLxe2x80x9d) which has an oscillator which runs at a given clock frequency, and which has a phase detector for comparing the phase difference between a PLL reference signal and the two different clock signals provided by the interface. In response to this comparison, the PLL outputs a single output clock signal at a frequency equal to twice the frequency of either of the two interface clocks. While this approach provides a single clock signal corresponding to the single data bus, it is well known in the PLL art that PLLs are subject to various drawbacks. For example, implementing a PLL that operates properly and does not fluctuate in its comparison or output functions may be considerably complex. As another example, implementing a PLL may be considerably expensive.
In view of the above, there arises a need to address the drawbacks of the prior art and the complexities arising from the gigabit internet standard or other systems providing a multiple clock, single data bus, interface, and this need is satisfied by the preferred embodiment described below.
In the preferred embodiment, there is a circuit for producing a single output data stream and a corresponding single clock signal. This circuit comprises an input for receiving a single input data stream, where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals, where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal, where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling the input data stream at the fast frequency, circuitry for outputting the sampled data as the single output data stream, and circuitry for outputting the single clock cycle in response to the fast clock signal. Other circuits, systems, and methods are also disclosed and claimed.